1. Field of the Invention
The present invention relates generally to a circuit for synchronizing asynchronous input data to a resolution which is greater than that offered by a clock which drives the circuit More particularly, the present invention pertains to a synchronizing circuit as described for asynchronous input data which represent a line of pixels of an image which must be displayed to a resolution which is more precise than that offered by a clock driving the display.
2. Discussion of the Prior Art
One straightforward approach toward improving the resolution of a display is to utilize a higher frequency clock (e.g. 64 MHz or 128 MHz) to drive the display, but that would entail or result in the necessity to use a higher frequency type of logic (e.g. ECL logic at the higher frequency rather than TTL at a 16 MHz frequency). As is known in the electronic arts, a higher frequency clocked circuit is a more expensive approach and also requires more precision in its design.
A second approach toward improving the resolution of a display is to generate a sequence of phase delayed clock signals and then select one optimum particular phase clock signal to achieve synchronization A variety of prior art references take this technical approach, including U.S. Pat. No. 4,713,621, U.S. Pat. No. 4,757,264, and U.S. Pat. No. 4,820,992. These prior art technical approaches often involve rather complex circuits which are expensive to build and implement.